Tiered IC Failure Analysis designed to meet customer needs while remaining cost effective
Sage provides a system of tiered turnkey IC Failure Analysis options designed to enhance feedback points, as well as partition work in such a way to manage cost and risk throughout an analysis:Level 1 – These non-destructive methods are recommended on all failures and will not alter the electrical properties of the device under test (DUT). This is designed to gather as much information as possible before proceeding to destructive testing, and may even result in finding the root cause of failure of certain fail types.
This level of IC failure analysis may include inspection steps such as:
- High resolution external optical documentation of package as received
- 2D or 3D micro-tomography X-ray of the device or system
- Scanning Acoustic Microscope (C-SAM)
- Time Domain Reflectometry (TDR)
- Curve tracing and simple electrical testing to verify the failure
- High-magnification, high resolution die inspection
All results are compiled into a comprehensive report.
Level 2 – Picking up where Level 1 IC failure analysis left off, Level 2 focuses on complex setups and isolation of the location in X and Y of the failure through the use of our advanced isolation tools. Commonly used tools include:
- Light Emission (PEM/LEM/EMMI)
- eXternally Induced Voltage Alteration (XIVA/LIVA/TIVA)
- Infra-Red (IR) fault isolation
Level 3 – Once a fault isolation location has been identified and reviewed by engineers to check consistency with the failure, the appropriate physical technique is chose. Destructive techniques such as:
- Parallel deprocessing (P-lapping)
- Mechanical cross-section of a potted sample or bare devices
- Dual-Beam FIB cross section of targeted area
are performed to supply high-resolution photos of the physical failure documented. For less straight-forward jobs (functional fails, multiple failing states, broad fault isolation locations etc.) it is imperative to verify and follow anomalous electrical responses throughout the levels of the die. By combining micro-probing, FIB editing, and AFM based nano-probing, we are able to verify electrical issues down through the gate level, for the most precise and targeted IC failure analysis.