Physical Defect/Failure Mechanism Discovery and Analysis

Physical Defect Analysis

Using our advanced tools and techniques, Sage Analytical Laboratories can analyze your devices in order to find the root cause of observed failures. Microelectronics geometries are continuously shrinking and varied and new cutting edge materials are being used. Therefore, the analyst needs to be aware of the ever-evolving failure mechanism they may encounter. Sage Analytical Lab’s prime mission is to drive towards root cause analysis and capture data and images of the source of a failure.
In many cases the failure mechanism is found to be the cause of the anomalous electrical signal. Other times, a voltage spike is the cause of the mechanism to name a few of the potential, numerous culprits. Whatever the cause of the physical defect, it takes a skilled analyst to anticipate what the failure mechanism may be and how to accurately analyze it within the ever changing technology.

A brief and by no means comprehensive list of some of the failure mechanisms that might be seen include:

  • Leakage at junctions or gates. Gate oxide pinholes are an example of a failure mechanism that may be caused by: high electrical fields exceeding the strength of the gate oxide breakdown ionic contamination, particle contamination, mechanical damage or uneven oxide growth
  • Metal traces anomalies. Metal trace anomalies can occur due to lithography issues, electromigration, from etching or from stress. A few examples of the physical mechanism may be metal bridging, filaments, or narrowing.
  • Opens can occur in a variety of ways. An open can be observed in a blown open metal trace. An open can occur with a via due to misprocessing either not being fully etched or with a severe misalignment. Electromigration is also a cause of opens with metal traces.
  • Shorts may be caused by EOS, bridging metal, bridging polysilicon, or even a metallic particle found within the inter-level dielectric material.
  • Functional failures are typically seen in the digital logic area and can include many of the aforementioned mechanisms.
  • Mishandling damage can be classically seen in ESD cases, mechanical damage of metal traces or damaged passivation, damaged wire bonds, and stress induced cracking at the package level.